Semiconductor wafers are typically processed by a sequence of thin film depositions and etches performed on the wafer or substrate. Various thin film layers may be patterned using photolithography techniques. Many modern photolithographic tools use a “step and repeat” exposure method in which a reticle forms identical patterns across the wafer in certain layers. In this process, each exposed layer has patterns that are aligned to the patterns below within tight tolerances. Each processed wafer typically includes an array of identical dies that that are subsequently diced up into individual dies. Each die may include circuitry and/or structures, e.g., MEMS structures, which may be used in devices.
Typically, semiconductor technology relies on die to die uniformity and high precision alignment between layers across the wafer. For example, process variations across the wafer or from layer to layer may sometimes adversely affect the functionality or performance of the individual dies. Thus, die level traceability is a highly sought after function by many semiconductor companies. Die level traceability allows one to identify the exact die location within a wafer from which the diced product was manufactured. For a number of reasons, it is often very useful for a manufacturer to know that exact location. For example, this information may be useful in identifying manufacturing issues and to help enhance yield, quality, and reliability. In addition, this information may enable further analysis, such as relating which processes and machinery formed particular dies that have been returned due to a malfunction. With this information, the manufacturer may be able to more readily and rapidly pinpoint and rectify manufacturing problems, enhance yield, and drive manufacturing and quality improvements.
To address die level traceability, some in the art use expensive test, trim, and process enhancements to identify each die location on the wafer. For example, many schemes have been developed including laser marking of scratch pads, fuse blowing at probe, programming non-volatile memory (NVM) on appropriate technologies, catalog identification using natural variation electrical signatures. All of these technologies have advantages and disadvantages in cost, process complexity, and process compatibility.